Introduction to Quartus II
Today we will use the Quartus II commercial FPGA design software to describe and simulate some digital circuits. We will begin with schematic entry and hierarchical design before switching to VHDL. We will also do some “mixed” design, combining several sub-circuits, some described schematically and some in VHDL.
1 Majority Voting Circuit
We will learn to drive the Graphic Editor program in Quartus by entering a schematic design of a simple Majority Voting Circuit. We will then simulate its operation assuming that it is built into an Altera FPGA from the Flex10k family.
1.1 Schematic Design Entry
Begin by creating a “quartus” directory on your hard drive where you can store all today’s design files—don’t store designs in the same folder as the Quartus installation files.
Start the “quartus” program and click File – New Project Wizard. In the “What is the working directory for this project” box browse to the Quartus folder you created. In the “What is the name of this project?” box type “maj_vote”. The software will automatically copy this name to the “what is the name of the top level entity…” box. Now click “Next >”. Click “Next >” again, since we don’t at present have any design files to add to the project—we will add these later. In the next page of the wizard select “Flex10k” in the “family” combo box and choose “EPF10k70RC240-4” in the “Available devices:” list. Note that this device has 3744 logic elements and 18432 memory bits. Now click “Next >” and “Next >” again since we will not be using any third party EDA tools. Click “Next >” once more to see a summary of the project settings, then click “Finish”.
You have now created a new project (which will eventually contain all the details of a complete FPGA design) with top-level entity “maj_vote”.
For our first design we will specify the circuit’s behaviour by means of a schematic diagram. Click “File – New…” and choose “Block diagram/schematic file”. Now select Save As on the File menu, and you should find that the software suggests “maj_vote.bdf” as the file name, since this is the name of the top-level entity you specified earlier. Save the schematic file.
You can now enter a design for a Majority Vote Circuit, shown in Figure 1. This circuit outputs a ‘1’ if two or more of the inputs are ‘1’ and conversely outputs a ‘0’ if two or more of the inputs are ‘0’.
Figure 1—Majority vote circuit
The gates and connectors are added to the schematic by right-clicking in the Schematic window and selecting “Insert – Symbol…”. In the “name” field of the resulting dialog box enter, respectively for each part, “and2”, “or3”, “input” and “output”. Connect the symbols together by dragging the mouse pointer between the connectors on the symbols. You can put a “crank” in any of the lines by stopping half way; and dragging a line to the middle of a previously drawn line adds a connection “dot” to it. Once you’ve entered one instance of a symbol you can “copy and paste” further instances, or use “repeat-insert mode”.
Double click the “PIN_NAME” on each I/O connector to enter the correct names.
Compilation and Simulation
Now we can compile the schematic design, which analyzes our design file and decides how to synthesize this in the chosen technology (in this case a Flex10k FPGA). In the project navigator pane choose the “Files” tab. You should find that Quartus has already added “maj_vote.bdf” to the project (click on the “+” sign to the left of “Device Design Files” in the Project Navigator to check. If it has not been added, right-click on “Device Design Files” and choose “Add/Remove files in project” and add “maj_vote.bdf” using the resulting dialog box.
Now choose “Processing – Start Compilation”. The software will then show progress in the “Status” pane. You will see that the compilation process includes several steps: “Analysis & Synthesis”, “Fitter”, “Assembler” and “Timing Analyzer”.
Next we want to build a set of test vectors for the circuit using the Vector Waveform Editor.Click “File – New…” and choose “Vector Waveform file” from the “Other files” tab. Right click in the left-hand pane of the “.vwf” window and choose “Insert node or bus…”. Click the “Node finder” button, choose “Pins: all” in the “filter” box and click “List”. Click the “>>” button to add all the found pins to the “selected nodes” list and click “OK” and “OK” again.
The vector waveform window will now show the inputs A, B and C and the output Y with default values (0 for inputs and X for outputs). Now click the Save button and accept the suggested “maj_vote.vwf” for the filename.
Now we can enter some test vectors. Right-click on “C” and select “Value – Count Value”. On the “timing” tab choose, multiply by 4. This fills C with alternating ‘0’s and ‘1’s, each “0-1” period being 4 grid blocks wide. Now fill row B with a similar bit stream, but “multiply by 2” and row A with “Multiply by 1”. You should now have a binary count sequence entered with C the most significant bit and A the least significant.
You can also group a number of binary inputs together—drag the rows A, B and C such that C appears in the top row and B in the middle, then select rows A, B and C together by clicking and dragging, right-click and select “Group…”. When prompted for a name enter “INPUT_CBA”, and enter “unsigned decimal” for the radix. You will now see the input represented as the sequence “0,1,2,3,…,7,0,…”. Try right-clicking INPUT_CBA and selecting “Value – Count Value” again. This time enter a Gray Code, multiply by 1. Observe that the counting sequence is no longer “1,2,3,4,…”. Now ungroup INPUT_CBA again and observe the Gray code outputs as individual waveforms. Revert to a binary count by a method of your choice, and save the “.vwf” file again.
Choose Tools – Options and under General – Processing select the “Overwrite Simulation input file with simulation results” tick-box and click OK.
Now start the simulator by selecting “Processing – Start Simulation”. The simulator report file will show your inputs and the simulated output, together with other information about the simulation. Switch to the “maj_vote.vwf” window to see the simulation output in more detail.
Note that the output does indeed go high when two or three of the inputs are high but that the output lags the inputs by around 19ns—this is a real circuit we’re simulating, with realistic values for the interconnect parasitics and gate delays obtained from the compiler.
We can save the output of the simulator in a “Table File”, choose “File – Save As…”and change the file type to“Vector Table Output File *.tbl”. View the table file in Notepad to see that it lists all the inputs and outputs every time a signal changes in value. This is the natural output of an Event Driven Simulator (more about that in the lectures…).
For the lab report produce copies of the schematic file and a table file produced for the simulation of your majority vote circuit. You should also include a printout of the screen showing the simulated output (Press <ALT> + <PRINT_SCRN> to copy the active window to the clipboard).
Switch back to the “maj_vote.bdf” file and choose “File – Create/Update – Create Symbol files for current file”. This make a symbol for your majority vote circuit. By combining two instances of your new symbol “maj_vote.bsf” with a two-input and (“and2”) gate in a new “.bdf” file “two_votes.bdf” build a circuit that has an output of ‘1’ when both sets of inputs have a majority of ‘1’s.
You will need to create a new project (with the new project wizard). Call your new project “two_votes”. You can put that project in the same folder as before, and safely ignore any warnings at this stage. Be sure to add “two_votes.bdf” to the project and select the same device as before (EPF10K70RC240-4). Compile your design.
Again produce a set of waveforms to test the circuit and generate a copy of the schematic file and some simulation output for your lab report. This time, just a screen dump of the output will be sufficient (no need for a table file every time). Paste a screen dump of the “Hierarchy” tab of the Project Navigator into the report as well. This shows the hierarchical structure of your design.
VHDL Design Entry
The VHSIC Hardware Description Language (VHSIC—Very High Speed Integrated Circuit) is an alternative way of specifying a digital IC. In this section we will re-visit the majority vote circuit, describing it in VHDL. We will also see one of the big advantages of Max+Plus II—we can build a “top level” schematic diagram and design a set of input waveforms as for the schematic capture case and apply those waveforms to a VHDL-specified circuit by creating a symbol for the circuit. This gets round the “testbench” problem in VHDL, where it takes longer to describe how you are going to test a VHDL design than it does to describe the design in VHDL in the first place. (More about testbenches later…)
Create a new VHDL file “.vhd” called “maj_vot2.vhd” again in the same directory as before. Enter the following text:
— VHDL implementation of a majority vote circuit
— Library contains standard VHDL logic types
— Entity defines inputs and outputs
ENTITY maj_vot2 IS
a, b, c : IN STD_LOGIC;
y : OUT STD_LOGIC);
— Architecture describes input/output relationship
ARCHITECTURE majority OF maj_vot2 IS
Y <= (a and b) or (b and c) or (a and c);
For your lab report produce a schematic showing the “maj_vot2” symbol and its connectors, some simulation output and a copy of the “.vhd” file.
Extend your VHDL to produce a 5-input majority vote circuit. Produce similar output as for the three input case.
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