Objective You will model and simulate some basic building blocks with Virtuoso Cadence and verify their functionality.
Important:- the entire lab should be done in Virtuoso Cadence
Details For all of the following problems, assume a capacitive load of 0.1pF.
1.(5 pts.) NMOS Transistor Demonstrate that nMOS transistor is a good conductor of 0’s and poor conductor of 1’s.
2.(5 pts.) PMOS Transistor Demonstrate that pMOS transistor is a good conductor of 1’s and poor conductor of 0’s.
3.(10 pts.) Transmission Gate Model a transmission gate and demonstrate its functionality. 4.(10 pts.) 2-input Multiplexer Using the above transmission gate, build a 2-input multiplexer and verify its functionality.
Deliverables
- Lab report using the template provided. PDF only.
- A
compressed zip file (.tar.gz file) containing all your schematic
diagrams as well as the simulated output. On Linux you can create a
compressed archive of a folder as follows:
prompt% tar czvf <folder>.tar.gz <folder>
For example, executing the following command will compress the inv folder.
prompt% tar czvf inv.tar.gz inv
Tips
1.Format your code well (just like you do in your C programs).
2.Do not discard your files. We will use them in later assignments.
3.A Word template will be provided which should be used for your report.
- Include
all schematic diagrams, simulation waveforms. For simulation results,
zoom in/out appropriately so that we can clearly see the input stimuli
and the output response.
0 comments