vlsi problems

VLSI Design

Show your work for all problems

Note: Unless otherwise stated, use only the following values or relationships, if needed, for solving problems. Do not use data or approximations from any other source:

μ_n = 690 cm² / v.s.μ_p = 230 cm² / v.s.ε_ox = 3.97ε_oε_o = 8.85 aF/μm

Long channel parameters:

V_DD = 5VV_THN = 0.8 VV_THP = 0.9VT_ox = 20 nmScale = 1 µm

Short channel parameters:

V_DD = 1VV_THN = V_THP = 0.28VT_ox = 1.4 nmI_on,n = 600 µA/µm

I_on,p = 300 µA/µmScale = 50 nm

You may use the results you find in one problem in another problem. You don’t have to repeat the same steps or calculations. Specify the units for all your calculations.

20 pts. 1. The following figure is intended to function as an N-input NAND gate. The POMSFETs are all identical and long channel with L_P =2µm and W_P = 9 µm. The NMOSFET is also long channel with W_N = 3µm. Assume that only one PMOSFET is on. Answer the following questions:

• If it is desired to have V_OH = 4.8V. In what region the PMOSFET will be operating and why? (3 pts.)
• With V_OH = 4.8V in what region the NMOSFET operates and why? (3 pts.)
• What is the general current equation for N-channel MOSFET in the region it is operating? Include V_OH in your equation if it applies. (2 pts.)
• What is the general current equation for P-channel MOSFET in the region it is operating? Include V_OH in your equation if it applies. (2 pts.)
• Calculate the value of L_N for the given V_OH by giving the general equal currents equations based on V_OH when both PMOS and NMOS are on.

Finding β_p (2 pts.), β_n in terms of L_N (3 pts.), and finally calculating L_N (5 pts.). (Total of 10 pts. for part ‘e’)

20 pts. 2. Find the switching point and noise margins for a 4-input NOR gate using long channel transistors. Assume W_N=10µm, W_P=20µm, and L=2µm.

15 pts. 3. Draw the waveform for the output of the following figure for two periods. The frequency of the signal applied to input is much less than the maximum switching frequency of the transistors. Specify the minimum and maximum voltages for the output in your solution.

V_DD

V_IN è

0

20 pts. 4. Draw the CMOS circuit diagram for the following function.

F= (AB’ + CDE’)’ + (A’ D’) (B’+ C’ E)’

25 pts. 5. Find the t_PHL and the t_PLH for the following figure assuming that short channel MOSFETs are used. Also, find the number and the multiplicative factor for sized inverters for minimum delay and specify the minimum delay.

C’_oxn, C_oxn, C’_oxp, C_oxp, C_in, C_out, R_n, R_p ç 1.5 pts. Each for total of 12 pts.

t_PHL and t_PLH for inverter ç 3 pts. each for total of 6 pts.

Calculation of N and A ç 2 pts. each for total of 4 pts.

Calculation of minimum delay ç 3 pts.