Please accept only if you know and have Virtuoso Cadence. Need D Flip-flop layout

Please accept if you have Virtuoso Cadence VLSI

For the following basic cells, draw the layout and verify the functionality by simulating the extracted netlist. You
should strive to get as compact a layout as possible without violating the design rules. The bounding box of a
layout is the smallest rectangle in which your layout can fit. In the lab report you must report the bounding box
area (width x height) of each cell.

Positive Edge Triggered D Flip-flop. Design a D-latch first and then cascade two of them with
appropriate clock signals.I need the ecact

I need the layout of the D Flip-flop on Virtuoso Cadence exact same as the on the images given below. Pls use the given inverter or NAND2 or your own