For above data path， modify the data path and control FSM so that only one adder is used (the adder needs to be shared among the 2 add operations) and still run at the rate of 1 output per 3 cc’s in steady state.
Hint: (1) need to use input muxes (controlled by the fsm) to the single adder to get the different inputs at different times
for the 2 adds. (2) Both adds need to be completed within the 3-cc delay window available to each pipeline stage (the 2
adds in a single adder will be one pipeline stage). (2) Need temporary register(s) that do not directly feed the multiplier but
instead feed r1 and/or r2 registers to store add outputs that are obtained in less than the 3 cc window as these o/ps should
not change multiplier inputs for 3 cc’s (after the previous load of r1, r2). (3) It is ok for some regs to have junk data before
steady state is reached (this is so in the original design above), but final o/ps in r4 starting from the 1st valid one have to be
correct. (4) Show the new FSM with the extra control signals needed (along with the original ones) with the RTL specified
for each state (except those that are purely NOP). Also label the new control signals clearly in the new datapath.
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