Hardware And Computer Organization

We need to use Easy68K to finish all of the questions

Q1. Cache and Memory mapping (6 points)

Suppose a byte-addressable memory has a total memory capacity of 2M bytes and the cache consists of 64 blocks, where each block contains 32 bytes.

1. Direct Mapping

1) Divide the bits into tag, block and offset bits.

2) What is the tag, line and offset for the address $123A63, in hexadecimal?

tag: 0x__________

line: 0x__________

offset: 0x__________

2. Fully Associative Mapping

1) Divide the bits into tag and offset bits.

2) What is the tag and offset for the address $123A63, in hexadecimal?

tag: 0x__________

offset: 0x__________

3. 4-way set associative mapping

1) Divide the bits into tag, set and offset bits

2) What is the tag, set and offset for the address $123A63, in hexadecimal?

tag: 0x__________

set: 0x__________

offset: 0x__________

Q2. Cache hit and miss (3 points)

Suppose we have a computer that uses a memory with a total memory capacity of 256 bytes. The computer has a 16-byte direct-mapped cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Here is the memory addresses in this exact order: 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, 0x6E, 0xB9, 0x17, 0xE2, 0x4E, 0x4F, 0x50, and 0xA4. The cache Tag and Block information has been filled out as shown below.

1. What is the hit ratio for the entire memory reference sequence (given in bold)?

2. What memory blocks will be in the cache after the last address has been assessed? Please fill in the Tag and Block first. Then, fill the actual address value for each offset location in the corresponding cell.

Q3. Virtual memory and cache (6 points)

Consider a processor with the following memory hierarchy:

256K virtual address space (byte addressable)

128K physical address space, each page (frame) has 32K bytes (byte addressable)

2Kbyte direct-mapped cache, a block (refill line) has 256 bytes

The machine uses a two entry TLB.

All replacement policies are LRU. There are two LRU stack.

The entry of these stacks are the page number of a virtual memory.

Note that all the values are represented as hexadecimal.

TLB

TLB LRU stack

Page Table

Mem LRU stack

cache

1. Split the bits of virtual address and physical address.

2. Split the bits in memory address based on the cache.

3. Suppose the processor has requested to access a memory in 0x32764 (which is virtual address)

1) Is it a page fault? Explain.

2) Show the changes of TLB, TLB LRU, page table and Mem LRU

TLB LRU stack

Page Table

Mem LRU stack

3) Show the changes in Cache.

Cache