Q3. (a) The following truth table represents the functionality of a full adder circuit. Design the full adder
circuit using 2-input Ex-OR, OR and AND gates. To minimize the design cost, your design should use
some part of the Sum circuit as a component in the Cout circuit.
(is in the file)
Q3. (b) The Full-Adder designed in part (a) can be used to design a binary adder circuit that can be used
to perform addition of two unsigned binary numbers. Using the Full-Adder of part (a), implement an 8-
bit binary adder circuit that would add two 8-bit unsigned binary numbers. To simplify the diagram, use
the Full-Adder as a block component (as shown in the above figure) in your design.
Q3. (c) Modify the design in part (b) such a way that the same circuit can be used to perform addition
and subtraction of two 8-bit signed binary numbers (note that in signed number representation, the
most significant bit is used as the sign bit). The circuit can be designed using either 2’s complement or
1’s complement technique of performing subtraction. I would like you to design the circuit using both
approaches. Draw and explain the operation of both of your circuits. Please note that your design should
include a control signal that would decide whether the circuit would perform addition or subtraction
with the given inputs in the system. Your circuit should also include an overflow output signal (v) to
indicate if there is any overflow in the addition/subtraction process.
Q3. (d) The major drawback of the circuit discussed in part (b) is that it requires a long propagation
delay before it produces the correct results. Since the Sum output (S) of each stage is dependent on the
Carry_in of all the previous stages, it behaves as a ripple/sequential adder circuit. One way to reduce the
propagation delay is to design a parallel adder circuit using the carry-lookahead technique (in which the
carry_in of each stage is made independent of the carry_out of the previous stage and dependent only
on the initial carry_in (i.e. the carry_in of the first stage), as discussed in pages 112-114 of your text
book). Using the carry-lookahead technique design an 8-bit unsigned binary adder circuit to perform the
addition of two unsigned 8-bit binary numbers. Note that you are allowed to use gates with maximum
input capacity of five inputs (i.e. the fan-in capacity is limited to 5-input). Clearly explain your design.
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