Electric Egineering latencies question

You are given the following hardware:

• A 16-bit PC register,
• An instruction memory with 1 read port (16-bit address input and 32-bit data output),
• A register file with 3 read ports and 1 write port (4-bit address inputs and 16-bit data output) where reading address 15 always gives zero
• An ALU with two 16-bit inputs that can perform all the operations listed above, with registers N and Z that store whether the last result is negative and zero respectively,
• A data memory with 1 read/write port (16-bit address & data inputs and data output),
• Additional multiplexers, gates, and pipeline stage registers as needed.

• Implement a single-cycle datapath for this architecture. [15 pts]

• Build a 6-stage pipelined datapath for this architecture. Given the following latencies, determine the minimum delay for each pipeline stage. You may ignore all other latencies. [15 pts]

• Write an example code snippet in this architecture that contains two different data hazards: one that can be resolved by forwarding and one that would require stalling the pipeline. [5 pts]