- Explain what is the function of this logic?
- What is the definition of critical path for a design?
- What is the critical path for this logic to compute “out” signal for this design?
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[19 pt] Problem 2
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- [5 pt] Write Verilog for a combinational module that adds 3 numbers (8-bit each) using two Adders. Sum=In1+In2, Out=in3+Sum. Extend the Sum and Out bit numbers to make sure the add can operate correctly.Make sure your module has inputs and outputs with the correct bit size defined.
- [4pt] Modify your Verilog to add D-flipflop registers with a clk signal in the Input and Output and explain where is the critical path in the module.
- [5pt] If each Adder takes 3 ns to give the output, how long it takes to have the final Out signal to be computed? What should be the clk Period value? Explain and Modify your Verilog to Pipeline the design such that the design can run at about 3ns clk period.
- [5pt] Draw a block diagram that uses only one Adder which has only two inputs and calculates Sum and then Out.
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[15 pt] Problem 3
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Explain What is the definition of Slack, Setup and Hold time in a digital circuit? Draw a timing diagram for a D-flipflop and clock signal show where are these numbers are coming from in the diagram.
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[40 pts] Problem 4 State Machine
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Design a circuit that computes the function yi=ci * bi * x (Two Coefficient Multiplier), where x is an input value (doesn’t change) and ci and bi are two coefficients stored in two memories each of them have 16 coefficients to be stored. x and ci and bi are all 8-bit numbers. When signal start goes high, the computation for yi starts which is sent to the output port as long as signal start is high. The circuit should minimize the area by using a single multiplier to compute the function.
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[4 pt] How many address bits is required to store all coefficients and what is the size of the memory for storing coefficients ci and bi?
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[2 pt] What is the output size of yi (in bits)?
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[5 pt] Draw a detailed block diagram of the circuit with inputs to each block, required size, signals and their connections. Explain how your circuit works.
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[3pt] Draw a timing diagram showing the important signal transitions.
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[4 pts] Write verilog for writing and reading from your memory (based on the signals that you defined).
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[10 pt] Design a state machine that computes the function
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- [2 pts] How many states are required?
- [2 pts] Draw state diagram for the state machine
- [6 pts] Write the verilog for the state machine (state logic and state transition and state register)
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[10] Write verilog for the datapath
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[20pts] Problem 5: Hamming Code Encoder and Decoder Design and Verilog
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- [7 pts] Encoder Module: Write verilog for the Encoder module that takes 8 bit binary Input and generates encoded binary output Encoded using hamming code that was explained in class. First explain how many bits you need for parity, which bits, and what are the equations.
- [3 pts] What is the length of total code word? Which bits are check bits and which one are data bits?
- [10 pts] Write the verilog for the module that checks if there is an error in the received data (You need to know how many bits is the received data). The verilog module has the received word as input and has two outputs error and error-bit. If there is any error, then the verilog module must locate the error bit and make the error signal to be 1 and send out the location of error-bit. Otherwise the error signal remains zero.
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